VHDL

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comp.lang.vhdl
X
Using REPORT statement during synthesis
  • xipn
Replies
5
Views
5K
Ben Jones
B
U
How to compile Xilinx Timing-Simulation library SIMPRIM under NC-Sim
  • uvbaz
Replies
2
Views
2K
uvbaz
U
S
VCD generation, ncsim, and primepower (first-timer)
  • sohaibm
Replies
1
Views
6K
sohaibm
S
G
How to check if ROM got inferred from synth reports
  • Guy_Sweden
Replies
3
Views
1K
Mike Treseler
M
S
Constrained-random verification.
  • Slawek Grabowski
Replies
2
Views
2K
Slawek Grabowski
S
M
verilog 'pullup' and VHDL
  • Mark McDougall
Replies
5
Views
13K
KJ
K
F
VHDL Vector Assignment
  • falcon734
Replies
0
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2K
falcon734
F
M
Type convertion when doing arimetic on intergers.
  • MLyngsie
Replies
2
Views
1K
MLyngsie
M
D
detecting overflow in arithmetic left shifter
  • dlamoris
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0
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2K
dlamoris
D
Z
FIR filter generic
  • Zorjak
Replies
1
Views
858
Jiri Plasil
J
M
Snthesis report
  • Mady
Replies
0
Views
665
Mady
M
V
why not use std_logic_arith?
  • vu_5421
Replies
6
Views
3K
Mike Treseler
M
4
A good solution wanted...
  • 48 bytes
Replies
1
Views
818
Brian Drummond
B
A
cross-post: newsgroup servers
  • Al
Replies
2
Views
994
Al
A
M
2 powerof (x) - where x fixed point value
  • MariuszK
Replies
11
Views
2K
wallge
W
E
Variables Synthesysable ?
  • ec
Replies
18
Views
1K
Mike Treseler
M
N
Generate sub-module (or not)
  • Niv
Replies
1
Views
615
Niv
N
B
ModelSim XE III/Starter 6.0d PROBLEM
  • blitzgeist
Replies
0
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3K
blitzgeist
B
P
VHPI Books
  • PlayDough
Replies
2
Views
3K
PlayDough
P
D
Synopsys's VMM and Mentor's AVM
  • Davy
Replies
11
Views
5K
googler
G
S
Memory synthesis using VHDL - Errors
  • strykaar
Replies
0
Views
1K
strykaar
S
R
Help with simple function call
  • Rishi Dhupar
Replies
1
Views
754
KJ
K
A
Assistance with INOUT Records
  • Analog_Guy
Replies
6
Views
2K
Paul Uiterlinden
P
D
Case Statement difficult
  • DPettit
Replies
0
Views
728
DPettit
D
I
addig delay to modelsim simulation
  • igal001
Replies
0
Views
1K
igal001
I
L
Synthesis
  • lightofspace
Replies
0
Views
980
lightofspace
L
L
VHDL synthesis
  • lightofspace
Replies
0
Views
957
lightofspace
L
G
Inferring block ram in Spartan II with non standard bus sizes
  • Guy_Sweden
Replies
2
Views
1K
David R Brooks
D
J
pre-layout simulation for lsi_10k netlist using ncvhdl
  • Jim
Replies
2
Views
2K
Jim
J
M
Synthesizable?
  • Moikel
Replies
3
Views
13K
Nicolas Matringe
N
D
problem with a shift register
  • dauzat.lilian
Replies
16
Views
2K
Mike Treseler
M
N
component statements within architecture statements
  • Neil Zanella
Replies
8
Views
2K
mfmehdi
M
M
Syntax check not catching error
  • marc rei
Replies
6
Views
819
KJ
K
Z
generic ROM memory help
  • Zorjak
Replies
3
Views
1K
zoran
Z
E
An implementation of a clean reset signal
  • Eli Bendersky
2
Replies
37
Views
3K
Eli Bendersky
E
T
Indexing a Configuration Specification
  • travcoe21
Replies
0
Views
760
travcoe21
T
L
Jedec file with FPGA advantage
  • lightofspace
Replies
0
Views
1K
lightofspace
L
A
unconstrained two-dimensional array?
  • andrea2
Replies
0
Views
1K
andrea2
A
A
Complex Bit Index Syntax, does this exist?
  • Alex
Replies
2
Views
710
Jonathan Bromley
J
T
CONV_INTEGER ERROR
  • ted.franklin3
Replies
4
Views
7K
Jim Lewis
J
M
OpenCores.org's I2C: Clock Stretching Support
  • markus_1401
Replies
2
Views
1K
markus_1401
M
D
Simulation problem in VHDL Simili from Symphony EDA package.
  • Daniel
Replies
3
Views
2K
pitarda
P
A
procedure and actual parameters
  • Al
Replies
3
Views
1K
Al
A
S
Conformal LEC of a VHDL design (RTL Vs Netlist)
  • sharatd
Replies
0
Views
4K
sharatd
S
L
Power analysis
  • lokesh_boddu
Replies
0
Views
780
lokesh_boddu
L
O
adding std_logic_vectors in vhdl
  • ohaqqi
Replies
3
Views
11K
Daniel Kho
D
S
Timing results without synthesis?
  • Sergey Katsev
Replies
4
Views
818
DualCore
D
J
Call for Participation Accellera VHDL Verification Features
  • Jim Lewis
Replies
2
Views
1K
Chris Foster
C
F
Synthesis / analysis takes long time.
  • flouger
Replies
1
Views
951
Thomas Stanka
T
S
16-bit barrelshifter.
  • Smops
Replies
4
Views
4K
Daniel Kho
D

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