VHDL

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comp.lang.vhdl
D
Don't know what to do: std_logic_1164.v93 has changed...
  • drseek
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0
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2K
drseek
D
S
synthesis of comparison operators
  • sybhs
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1
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897
Mike Treseler
M
K
Competent VHDL Simulators?
  • Ken Asbury
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5
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2K
Ken Asbury
K
R
best way to code an adder
  • Roger Bourne
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12
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5K
Andy
A
S
Problem with JTAG_SIM_VIRTEX4
  • Stefan Hauf
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1
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898
Stefan Hauf
S
A
error
  • ashu
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4
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927
Mike Treseler
M
P
Free VHDL Simulator(s) ..?
  • pbdelete
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3
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5K
pbdelete
P
M
Bit reversal and IRC
  • M. Norton
Replies
11
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4K
Mike Treseler
M
A
To_stdlogicvector
  • ashu
Replies
3
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15K
Ralf Hildebrandt
R
S
reading from files
  • shikha
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4
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905
chetaneklaspur
C
P
Arbiter for the wishbone bus
  • Pooja
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1
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4K
Mark McDougall
M
B
Quartus v6.0 problem
  • Boris Ozegovic
Replies
1
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1K
Boris Ozegovic
B
S
simulation working , synthesis causing problems
  • sandeep
Replies
0
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844
sandeep
S
S
Xilinx vhdl counter recognised as register
  • Sanka Piyaratna
Replies
6
Views
4K
Dave Pollum
D
D
Verification by Non-HDL(C++/Java)??
  • Davy
Replies
4
Views
1K
mmintz
M
A
HDL AUTHOR and SLL problem!
  • a_Conan
Replies
5
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3K
Hans
H
I
Shift Register Problem
  • Indroneel Ganguly
Replies
9
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3K
Indroneel Ganguly
I
P
system c/specman e tutorials
  • Pow
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1
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5K
avidan_e
A
P
Easy way to define lots of zeroes
  • Peter Bluer
Replies
4
Views
972
Peter Bluer
P
O
USART help
  • Ocean
Replies
1
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985
Ocean
O
H
Mapping a std_bit_vector to a record
  • hans.huebner
Replies
18
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6K
KJ
K
L
How to simulate the connection of to bidir ports ?
  • lundril
Replies
2
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1K
KJ
K
C
Logical gates tester
  • cyrak
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0
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910
cyrak
C
C
problem with data flow modelling
  • crackle24
Replies
3
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1K
Andy
A
A
optimization of vhdl code
  • ashu
Replies
5
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6K
john
J
S
4 level to 2 level round robin arbiter
  • ssahota
Replies
2
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4K
Pooja
P
A
for language experts: Constants defined in an entity visible in all deeper inner entities
  • albert.neu
Replies
7
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1K
albert.neu
A
L
Cross clock domain control signal convey
  • legendbb
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0
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1K
legendbb
L
L
Question to resolved signals, transport delay
  • lundril
Replies
6
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2K
Marcus Harnisch
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J
nesting counters
  • john
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0
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719
john
J
G
A problem with crc-32 check
  • grimreaper
Replies
2
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3K
grimreaper
G
L
function call(help)
  • leon86
Replies
0
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659
leon86
L
L
function(help!)
  • leon86
Replies
0
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650
leon86
L
H
std_logic resolution
  • Hilko
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11
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7K
Hilko
H
R
DATAIO ABEL
  • Ron
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4
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1K
Ron
R
W
The differences between behaviors of 'std_logic_vector' and 'unsigned'
  • Weng Tianxiang
Replies
2
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1K
Weng Tianxiang
W
W
Problem :(
  • Wojtek
Replies
7
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1K
lundril
L
J
Records & Synthesis
  • Jeremy Ralph
Replies
3
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1K
lundril
L
V
How to model a buffer in VHDL
  • vishallko31
Replies
6
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14K
KJ
K
S
Design with IP-Cores on different FPGAs
  • sthauf
Replies
3
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964
sthauf
S
V
Modeling a quantiser in VHDL (synthesisable circuit)
  • vishallko31
Replies
0
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950
vishallko31
V
G
primetime
  • Gervacio
Replies
0
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774
Gervacio
G
M
vhdl coding and glitches that my result
  • mmali69
Replies
0
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902
mmali69
M
L
help on coding pls~
  • leon86
Replies
2
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783
Jeremy Ralph
J
J
Combinational feedback loops
  • john
Replies
13
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4K
Mike Treseler
M
J
Failing paths
  • john
Replies
0
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639
john
J
K
DRAM controller???
  • Kenneth
Replies
2
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4K
radarman
R
H
optimizing my design
  • harikris
Replies
3
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739
Thomas Stanka
T
B
Needed good website on DES algorithm
  • bxbxb3
Replies
1
Views
941
Roberto Gallo
R
A
fpga programming
  • ashutosh_k
Replies
1
Views
814
john
J

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