VHDL

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comp.lang.vhdl
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VHDL Variables Question
  • cobolt_dink
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0
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4K
cobolt_dink
C
N
[AHDL]
  • news1.ustronie.pw.edu.pl
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3
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2K
Andy Peters
A
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VHDL project required
  • nitindhamija
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0
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1K
nitindhamija
N
R
VHDL integer signal in tri-state
  • Roberto Gallo
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3
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6K
Ralf Hildebrandt
R
D
stdio_h.vhd and 0x prefixes
  • Dal
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4
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2K
Amal
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J
character to std_logic value
  • jahaya
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2
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1K
Dal
D
M
RAM simulation (HM6116P)
  • Moikel
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2
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3K
Dave Pollum
D
A
for language experts: RANGE TYPE
  • albert.neu
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3
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1K
Mike Treseler
M
T
vhdl 200x status?
  • tkvhdl
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14
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2K
tkvhdl
T
S
Converting std_logic_vector to integer
  • skilambi
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3
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17K
David Binnie
D
A
The assign statement in verilog doesnt generate a module in design architect
  • aushitha
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0
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1K
aushitha
A
H
Verilog book recommendation
  • hdl_book_seller
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1
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889
gabor
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F
VHDL Generics problem when simulating SDF with Scirocco
  • Fazela
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1
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1K
Ajeetha
A
A
for language experts: generic lower in list may reference generics higher in list
  • albert.neu
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4
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1K
Hans
H
A
Interesting XST warning
  • Andy Peters
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9
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3K
Mike Treseler
M
M
MCU clock divider vs. VHDL divider
  • Matt Clement
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3
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5K
Marcus Harnisch
M
A
real to time
  • Attila Csosz
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2
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14K
Brian Drummond
B
Y
Modelsim Simulation
  • Yaseen Zaidi
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1
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1K
Abs
A
S
What is the best way to clock data in on one clock edge and out on another?
  • simon.stockton
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4
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2K
Peter Alfke
P
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vhdl cpu emulator (any interest?)
  • nkmlists
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1
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2K
D Stanford
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A
Non power of 2 natural counter - neat alternatives to mod operator?
  • Andrew FPGA
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8
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7K
Andy
A
J
character to std_logic value
  • jahaya
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3
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9K
Mike Treseler
M
A
VERIFICATION TESTPLAN
  • Abs
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0
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971
Abs
A
2
FSM for parallel port
  • 2door
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0
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909
2door
2
S
how to write a conditional assignment over generic or constant?
  • sm.soimu
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2
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7K
sm.soimu
S
S
different variable in generate statement
  • sanborne
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7
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1K
Weng Tianxiang
W
O
FPGA-programmers and VHDL on OS-X?
  • Oliver Bandel
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4
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15K
Phil Tomson
P
A
ram model
  • ashutosh_k
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2
Views
1K
Andy
A
C
Problem with shift operation
  • Chandru.Kundagol
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3
Views
862
jens
J
R
Package texio - writeline and deallocate
  • RobertP.
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1
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2K
john Doef
J
C
Problem with operation
  • Chandru.Kundagol
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4
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929
Andy
A
R
twos complement data
  • redstripe
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3
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3K
Andy
A
A
Fake vcc and gnd
  • aushitha
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2
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2K
aushitha
A
A
Generate state with non-static range?
  • Alex
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10
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2K
Alex
A
S
Map net into BRAM
  • SmiG
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2
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880
radarman
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array
  • daniele
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7
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1K
radarman
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Y
State machine glitch
  • yaseenzaidi
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4
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2K
radarman
R
B
basic VHDL question
  • Brad Smallridge
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10
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3K
Brad Smallridge
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V
isolating cells, clamps
  • vicky
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2
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790
vdvalk
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S
Is there anything fundamentally wrong with this code?
  • simon.stockton
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5
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1K
KJ
K
M
UART with fractional baudrate generator ? Or fractional baudrate generator alone
  • Martin Maurer
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3
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8K
Peter
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N
integer'image string width
  • Nicolas Matringe
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5
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11K
Mike Treseler
M
C
How to convert from netlist to Boolean expression - PLEASE HELP
  • cpptutor2000
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0
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2K
cpptutor2000
C
Y
Boolean as port type
  • Yaseen Zaidi
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1
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1K
Mike Treseler
M
D
How to clarify algorithm of hardware(HDL)?
  • Davy
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2
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1K
Keith
K
A
Constant conversion (natural to std_logic_vector)
  • a1_nocrap_exh
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10
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18K
Andy
A
F
SPI Problem
  • Fizzy
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4
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4K
Andrew FPGA
A
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Xilinx WebPack 8.1i "desoptimization"
  • Rafal Pietrak
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5
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3K
Mike Treseler
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2
SPP for Digilab
  • 2door
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1
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878
charles.elias
C
D
Best way to address block ram?
  • dhbrewer
Replies
3
Views
2K
hdlcohen
H

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