VHDL

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comp.lang.vhdl
M
test bench creation
  • manjunath.rg
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3
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892
beeraka
B
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Implementation Problem.
  • tcl
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12
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2K
Rod Pemberton
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VHDL 2002 vs VHDL 1993
  • dude
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1
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3K
Nicolas Matringe
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Problem with buttons - sounds old, but...
  • Pleg
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10
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1K
Benjamin Todd
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need correction 16 bit risc processor code
  • selva991
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4
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1K
Uncle Noah
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help needed on 16 bit risc processor in VHDl
  • selva991
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0
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3K
selva991
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A
multiD-vhdl: Multi Dimensional Arrays (allowing generics on each dimension) for VHDL (including port
  • albert.neu
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2
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12K
Jim Lewis
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System Tasks in VHDL
  • kedarpapte
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7
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5K
Jim Lewis
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Self-check Testbench Learning
  • Davy
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0
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1K
Davy
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D
Get the carry with add operator
  • Damien Bardon
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5
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11K
Mike Treseler
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A
Program for drawing clock cycles?
  • Allan Herriman
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2
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2K
Thomas Thorsen
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CoolRunner 2 CPLD
  • Duccio
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2
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4K
Klaus Falser
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GHDL or FreeHDL?
  • Guillaume
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10
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11K
Weng Tianxiang
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SMTP
  • leibnizster
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0
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855
leibnizster
L
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Different VHDL-interpretation between Xilinx ISE/ModelSimXE?
  • Thomas Thorsen
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2
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8K
Thomas Thorsen
T
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How is Synopsys DC 2004.06-SP2's capability in synthesizing large designs.
  • Novice
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5
Views
987
michaelst
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C
Xilinx ISE collapsing registers, how can I prevent it?
  • creon100
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5
Views
2K
Dave Pollum
D
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hello friend i facing a probelm to create code for 8 bit microprocessor
  • honeysangam
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3
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2K
David Binnie
D
S
NCVHDL Compilation....plz help
  • savitha.john
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0
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3K
savitha.john
S
C
VHDL newbie question about wires???
  • coxsterdillon
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5
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3K
Peter
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V
need FIFO material
  • vishnu
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0
Views
854
vishnu
V
I
Using Prime Time To Find All The Paths Of A Seq. Cir., Not Only the Critical Ones
  • ilterisderici
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0
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1K
ilterisderici
I
F
Can Primetime work without constraints?
  • Fazela
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0
Views
808
Fazela
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loop filter in vhdl
  • jalaram
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1
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2K
mk
M
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"ERROR:Xst:1548 - file.vhd line xx: Negative range in type of signal <h> is not supported"
  • Santosh
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0
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1K
Santosh
S
C
Help
  • craigs2
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0
Views
979
craigs2
C
D
CoolRunner 2 CPLD
  • Duccio
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0
Views
974
Duccio
D
A
Modelsim Delta Races
  • Andrew Greensted
Replies
4
Views
6K
Thomas Stanka
T
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verification
  • Sarah
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2
Views
1K
Andy Peters
A
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processor bus tristate at two places
  • praveen.kantharajapura
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1
Views
909
radarman
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M
Request for feedback: proposed new Perl modules to aid VHDL projects
  • Michael Attenborough
2
Replies
22
Views
4K
Mike Treseler
M
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How to specify a package in Xilinx 8.1i
  • Weng Tianxiang
Replies
1
Views
4K
Weng Tianxiang
W
M
PCI wishbone can bus
  • mungam
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1
Views
1K
Mark McDougall
M
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How to specify a global package in Xilinx 8.1i
  • Weng Tianxiang
Replies
1
Views
835
Mike Treseler
M
I
Verification Methodology Manual for SystemVerilog examples
  • imavroid
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0
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1K
imavroid
I
A
Intel 4004
  • asapanya
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6
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2K
Eric Smith
E
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Reading multiple file
  • ndutta
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1
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1K
Mike Treseler
M
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READ FROM FILE
  • sarma.nedunuri
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2
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3K
sarma.nedunuri
S
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what's the differences between the behavioral model and the RTLmodel?
  • risingsunxy
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7
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10K
Weng Tianxiang
W
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Enumeration types and bits
  • Pleg
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5
Views
1K
KJ
K
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VHDL design hierarchy, modules/componets and I/O pins
  • Rafal Pietrak
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10
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5K
Mike Treseler
M
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Pin Locking on a FPGA
  • bob_shuler
Replies
5
Views
2K
Weng Tianxiang
W
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Dual data rate in Xilinx WebPACK 7.1
  • Rafal Pietrak
2
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22
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2K
Mike Treseler
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A
exporting variables
  • AB
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1
Views
725
Mike Treseler
M
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Inferring RAM from array of records
  • jtw
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1
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1K
Mike Treseler
M
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"when" assignments in process ?
  • Sylvain Munaut
Replies
7
Views
1K
Weng Tianxiang
W
A
Power consumption estimation
  • AG
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0
Views
1K
AG
A
M
Clock Process?
  • Moikel
Replies
5
Views
958
ALuPin
A
M
"global" signal in VHDL
  • manu
Replies
7
Views
13K
Barry Brown
B
A
Unconstrained array of unconstrained vector.
  • Amal
Replies
5
Views
12K
Brandon
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