VHDL

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comp.lang.vhdl
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Query related to division of 1.122 in mentioned code.
  • Kritika Bhardwaj
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1K
Kritika Bhardwaj
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verilog hdl
  • shachi
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1K
shachi
S
C
Illegal sequential statement (VHDL)
  • chiraz
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2K
chiraz
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lms algorithm code
  • alok das gupta
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1K
alok das gupta
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Mixer-Unit on Altera DE2-115 Cyclone IV
  • Larinayo
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1K
Larinayo
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VHDL Subtraction two’s complement
  • Alenx
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0
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3K
Alenx
A
A
2 flip-flop synchronizer
  • andys86498
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1
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3K
netguy63
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Xilinx ISE, expression not globally static inside generic map
  • Zo Ki
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0
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1K
Zo Ki
Z
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ASIC RTL and FPGA RTL
  • Anand P Paralkar
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2
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9K
Yasir Khizar
Y
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How to use ufixed when it involves multiplication a number of times?(VHDL question)
  • Anwesa Roy
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2K
Anwesa Roy
A
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Input ports in VHDL of type string and Boolean
  • Razn_957
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0
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2K
Razn_957
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Issue with simulation time - Modelsim PE Student 10.4
  • Rashnak
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1
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2K
Rashnak
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miroslavasadov
pls help me ; vhdl;
  • miroslavasadov
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0
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2K
miroslavasadov
miroslavasadov
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I need a VHDL code
  • Moh
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0
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2K
Moh
M
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and operator overloading
  • eladsolomon
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2K
eladsolomon
E
I
1:8 demux behavioral and structural modeling
  • Ibra1950
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1
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8K
Ibra1950
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Floating point library RC
  • Gonzalo
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0
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1K
Gonzalo
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VHDL 2005, VHDL93 and FPHDL
  • vijay
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3
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2K
Gonzalo
G
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Minimum period: No path found
  • kiran77
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0
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2K
kiran77
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Shift left register using VHDL shift operator : sll trouble
  • Anviori
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0
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2K
Anviori
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4 bit two flipflop sychronizer
  • Bhakti Dedhia
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0
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1K
Bhakti Dedhia
B
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FPGA for Frequency Divider
  • _Jaiko007
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0
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1K
_Jaiko007
J
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geting error as unxpected symbol read: ". in array initialization
  • mrunal
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0
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2K
mrunal
M
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  • Poll
Is my port map syntax right???? i am not able to find the proper guidance for the error in any book
  • keerthi_raj
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0
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1K
keerthi_raj
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J
Send data from MATLAB to FPGA through USB
  • jose de arimatea
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0
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2K
jose de arimatea
J
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vhdl
  • rupakala
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0
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2K
rupakala
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help me to code vending machince with following specification
  • SHAJITH
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0
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1K
SHAJITH
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suppress all Warnings and errors in Modelsim simulation
  • neo_anderson
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1
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15K
Naveed Mahmud
N
C
Implementation a SVM ( SVPWM) in FPGA with VHDL
  • Colllins Nana
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0
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3K
Colllins Nana
C
H
space vector modulation fpga
  • hasanabouali
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13
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8K
Colllins Nana
C
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error in serial right operation in modelsim10.4a
  • maneesha zakka
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0
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2K
maneesha zakka
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nine code compression
  • sowndarya
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0
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1K
sowndarya
S
S
alternative variable length code
  • sowndarya
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0
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1K
sowndarya
S
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Vhdl code for octal to binary conversion
  • Jaison jacob
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0
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3K
Jaison jacob
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I want VHDL code for n x n matrix multiplication without using pipelining
  • pritam
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0
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2K
pritam
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merge sort
  • divyavani
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0
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2K
divyavani
D
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how to generate a Staircase wave using vhdl code?
  • maheshr
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0
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2K
maheshr
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textio error
  • Pasacco
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4
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6K
razies
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stepper motor
  • Sweta Dauhawoo
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0
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2K
Sweta Dauhawoo
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S
Gray Code
  • sarovarc
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2
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3K
Sweta Dauhawoo
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BPSK COSTAS LOOP DEMODULATOR
  • Minesh Darji
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0
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2K
Minesh Darji
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wimax interleaver
  • rkavipriya
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0
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2K
rkavipriya
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Divyesh Patel
VHDL program error
  • Divyesh Patel
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2
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6K
cmelias
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E
problem executing testbench. error in coding
  • ezzyrul
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1
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2K
cmelias
C
S
VHDL
  • Sohaib
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1
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1K
cmelias
C
T
VHDL into a simulink model
  • Tomer Gidony
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6
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7K
ram2010
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A
Multiplication VHDL
  • Ayoub
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4
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3K
fredrick
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Problem with Fix_std
  • Luca
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3
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1K
fredrick
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using FIX_STD
  • Ved
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1
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1K
fredrick
F
N
Hash 256 function
  • niv
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0
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952
niv
N

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