VHDL

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comp.lang.vhdl
Q
2bit- comparator -- VDHL Error in ModelSim about this Script.
  • quaere1verum
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3
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1K
quaere1verum
Q
A
Kode-da-Circiut Online VHDL Competition
  • Ajit Mathew
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1
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1K
Ajit Mathew
A
K
Help using generate statement
  • koyel.aphy
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4
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1K
Paul Uiterlinden
P
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These no else statements generate latches?
  • fl
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2
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1K
Andy
A
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fpga IOB
  • niyander
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2
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5K
Andy
A
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Multi Valued logic simulation using VHDL?
  • Guru Prasad
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2
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2K
Lokesh Kanna
L
C
Calculating Percentages in VHDL?
  • Cory Shol
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3
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2K
Andy
A
V
Resolution func in the initialization
  • valtih1978
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15
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1K
Paul Uiterlinden
P
B
Active-HDL: all writes to STDOUT are prefixed with "KERNEL:"
  • Brian Davis
Replies
3
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1K
Brian Davis
B
S
VHDL port type conversion
  • sugobj
Replies
0
Views
883
sugobj
S
J
simulation help
  • jeffreywhite2011
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2
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1K
jeffreywhite2011
J
R
VHDL design flatten compilation
  • ronhk25
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7
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2K
ronhk25
R
R
or_reduce for array of std_ulogic_vectors REVISITED
  • Richard Nicholas
Replies
8
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2K
Richard Nicholas
R
T
Large array
  • TON2
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0
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806
TON2
T
N
Receiving part of a UART
  • Nojman
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0
Views
988
Nojman
N
G
How to assign a hex or decimal value to a std_logic_vector of length19 bits?
  • gabor
Replies
6
Views
72K
mahfoudh
M
G
structural VHDL
  • gg
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0
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1K
gg
G
A
Simulink/Modlelsim cosimulation error
  • Ata
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0
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2K
Ata
A
P
How to load multiple test vector files, where the filename come fromgeneric parameters?
  • py
Replies
3
Views
972
Nicolas Matringe
N
S
barcode scanner program display with android..
  • Saifullah Hasshim
Replies
2
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1K
John Speth
J
F
Audio Codec DE2-115
  • FPGA_guru
Replies
1
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5K
olivierace13
O
A
How to use SDRAM Vhdl with DE2-115??
  • annna
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0
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2K
annna
A
A
Help creating SDRAM circuit
  • annna
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0
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1K
annna
A
A
constrained random verification of a fifo - with OSVVM
  • alb
Replies
1
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1K
Jim Lewis
J
T
inequality with std_logic_vector in what package is defined
  • thierrybingo
Replies
1
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1K
Jim Lewis
J
L
racing condition in vhdl
  • lazyant118
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0
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1K
lazyant118
L
H
Carry Save Adder (CSA) Verilog code
  • humble_Stuff
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3
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14K
alb
A
A
compact bus description
  • alb
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17
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1K
alb
A
R
VHDL signal and variable assignment
  • ramy
Replies
7
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2K
Andy
A
R
I need an or_reduce for an array of std_logic_vectors
  • Richard Nicholas
Replies
11
Views
2K
alb
A
K
Verilog Binary Divider
  • Kristo Godari
Replies
2
Views
6K
Nikolaos Kavvadias
N
A
timing verification
  • alb
2
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22
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3K
Mike Treseler
M
A
combinational loops
  • alb
2 3
Replies
54
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5K
alb
A
S
DIVIDE-BY-TWELVE DECODE COUNTERS( SN7492)
  • saeed omer
Replies
3
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1K
Rob Gaddi
R
M
Reflexions about a new HDL language
  • Mister_J
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1
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1K
simguru
S
M
VHDL sharing components?
  • Matt Johnson
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1
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1K
GaborSzakacs
G
D
Partnership Request
  • Dan Wawa
Replies
2
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825
GaborSzakacs
G
S
FIR Filter Transposed Form VHDL
  • Ste_ee
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12
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2K
Ste_ee
S
R
VHDL vs. System Generator, et al.
  • Robert G. Kaimer Jr.
Replies
12
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6K
ngcolin
N
F
How to design 4 bit 4:1 multiplexer
  • Faisal Kabir
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1
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1K
Jim Lewis
J
R
fifo reading
  • revkarol
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3
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1K
revkarol
R
V
How did Ashenden know about STD_INPUT?
  • valtih1978
Replies
7
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1K
Andy
A
A
bit slice in vectors
  • alb
Replies
4
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1K
Andy
A
B
vhdl-mode emacs - what does creating a Project do?
  • BlackHelicopter
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1
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1K
BlackHelicopter
B
B
ModelSim 'vmake' and bash is not generating properly formatted Makefile
  • BlackHelicopter
Replies
0
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2K
BlackHelicopter
B
A
vhdl & verilog simulation
  • alb
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4
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1K
pini
P
A
autonomous monitors
  • alb
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2
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1K
alb
A
V
return the (value of) assignment
  • valtih1978
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2
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1K
Tim McBrayer
T
A
data type choice
  • alb
Replies
7
Views
1K
KJ
K
R
Possible Quartus Bug
  • Rob Gaddi
Replies
4
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2K
Tricky
T

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