VHDL

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comp.lang.vhdl
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Verilog: Why the "maxcount" cannot keep its max value but changeswith the "count"?
  • kaiyutony
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4
Views
1K
rickman
R
B
SPI; simulating an input (rx)
  • Brandon Spiteri
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8
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1K
KJ
K
C
Parallel load register 4 bit without using instantiation
  • chirag.nitb
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1
Views
1K
rickman
R
P
Code owuld compile before, now doesnt recognise '='
  • professor_dikweed
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0
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1K
professor_dikweed
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O
Writing testbench tools. Suggestions?
  • o pere o
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7
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1K
Andy
A
A
code vhdl
  • Ayoub
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1
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2K
Rob Gaddi
R
A
demande plz
  • Ayoub
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3
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911
Nikolaos Kavvadias
N
A
Array of Modulation BPSK
  • Ayoub
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0
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1K
Ayoub
A
A
Array VHDL
  • Ayoub
Replies
3
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1K
Tricky
T
T
Can I replace this procedure with a function (VHDL 2008 problem)?
  • Tricky
Replies
6
Views
1K
Tricky
T
N
ASIC gate count estimation
  • nmatringe
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11
Views
17K
Nikolaos Kavvadias
N
A
Help code VHDL
  • Ayoub
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2
Views
1K
Ayoub
A
M
VHDL to SystemC
  • moogyd
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3
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2K
moogyd
M
A
PC function code
  • Amr Kassab
Replies
0
Views
942
Amr Kassab
A
A
erreur VHDL 2
  • Ayoub
Replies
1
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841
alb
A
A
erreur VHDL
  • Ayoub
Replies
3
Views
2K
Sean Durkin
S
A
FFT CALCULATION USING DISTRIBUTIVE ALGORITHM.
  • ajit yadav
Replies
2
Views
991
KJ
K
S
code question
  • sk3ptic
Replies
2
Views
1K
sk3ptic
S
T
Design toplevel module as schematic?
  • Tobias Baumann
2
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22
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3K
Anssi Saari
A
R
Cache Memory
  • rykardu
Replies
1
Views
2K
belchel01
B
V
Separate elaboration and parsing
  • valtih1978
Replies
6
Views
1K
valtih1978
V
S
conv N/A _ with_Virtex5
  • Salah Kortli
Replies
0
Views
814
Salah Kortli
S
S
Virtex-5 clocking
  • Saul Bernstein
Replies
5
Views
2K
salahc4
S
Y
VHDL code error
  • Youssef Ahmed
Replies
10
Views
1K
Andy
A
G
VHDL Synchronizer Function
  • genogiapasetti
Replies
2
Views
2K
Dio Gratia
D
A
[cross-post][long] svn workflow for fpga development
  • alb
Replies
7
Views
1K
alb
A
O
How dofor using generate or loop for this process ?
  • Olivier Dir
Replies
3
Views
1K
Daniel Kho
D
Y
how to avoidind multisourcing on signal
  • yogesh malekar
Replies
5
Views
994
Daniel Kho
D
A
[cross-post]path verification
  • alb
2
Replies
31
Views
2K
HT-Lab
H
S
verilog questions
  • sandhya pochiraju
Replies
1
Views
1K
rickman
R
R
22v10
  • rkdkkr
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0
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1K
rkdkkr
R
R
sensitivity list
  • rkdkkr
Replies
0
Views
737
rkdkkr
R
A
Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
  • alb
Replies
7
Views
3K
Andy
A
O
precompilation 'Vhdl' syntax
  • olivier90dir
Replies
1
Views
846
Olivier Dir
O
B
Integers which are more than 32 bit
  • bipper
Replies
1
Views
1K
Paul Uiterlinden
P
N
VHDL simulator supporting SCE-MI or vendor's DPI?
  • Nikolaos Kavvadias
Replies
1
Views
1K
HT-Lab
H
E
Need help designing a circuit in Verilog
  • eithriad
Replies
2
Views
787
Nikolaos Kavvadias
N
N
Multi-function, universal, CORDIC IP available from the OpenCores website
  • Nikolaos Kavvadias
Replies
0
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1K
Nikolaos Kavvadias
N
L
loop 10000 iterations limit in quartusII.
  • Luis Cupido
Replies
6
Views
1K
Daniel Kho
D
J
problem with unsigned vs std_logic_vector
  • jlodman
Replies
11
Views
2K
Andy
A
R
Execution of a process without an event occurring in its sensitivity list
  • Raja Harsha
Replies
4
Views
1K
Daniel Kho
D
J
getting the range from a member of a record.
  • jlodman
Replies
5
Views
2K
Andy
A
F
Can wild letters be used in case statements?
  • fl
Replies
8
Views
1K
HT-Lab
H
C
VHDL verification using Python via VHPI
  • Chris Higgs
Replies
0
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2K
Chris Higgs
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T
How to instantiate a verilog block inside a VHDL entity?
  • thunder
Replies
4
Views
2K
Daniel Kho
D
F
Why does this if process wrong?
  • fl
Replies
5
Views
1K
Nicolas Matringe
N
F
Questions about negate a negative number
  • fl
Replies
1
Views
1K
GaborSzakacs
G
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help regarding an open source
  • koyel.aphy
Replies
4
Views
965
koyel.aphy
K
F
pipeline and low power relationship
  • fl
Replies
1
Views
835
goouse99
G
F
How to implement an irragular table?
  • fl
Replies
2
Views
1K
fl
F

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