VHDL

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comp.lang.vhdl
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  • valtih1978
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10
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valtih1978
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TCPdump format
  • tomerger
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1
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pini
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addition not work in vhdl
  • marcin00022
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6
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pini
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concurrent signal assignment in a process
  • alb
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3
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Andy
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parametric vector slices
  • alb
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729
Andy
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abstracting the client/server protocol
  • alb
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5
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Andy
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Equations in Vector Range Definitions
  • guyanalog
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2
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868
Andy
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verify the IP filter using vhdl linked lists
  • bknpk
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1
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pini
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Matrix multiplication
  • mhamzahab
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2
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himu8055
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RFC: VHDL testbench enhancements
  • Jim Lewis
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7
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pini
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Scoreboard and Checker in Testbench?
  • Davy
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16
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9K
pini
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confusion about delta time
  • sensor
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4
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Paul Uiterlinden
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How to give one clock cycle in VHDL testbench?
  • Chris Waugh
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5
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goouse99
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Fixed Point + Math Package/Library Verilog/VHDL
  • abdkahnz
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1
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goouse99
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Opening and closing a file in a testbench
  • Nemesis
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2
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bknpk
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AHB/APB graduate project
  • bknpk
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0
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bknpk
B
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ethernet on spartan 3an
  • revkarol
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5
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bknpk
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Is a block spoof IP filter in hardware (VHDL design) is required
  • bknpk
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0
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931
bknpk
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New VHDL Project
  • shankarmishra124
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3
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871
bknpk
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Any one who can help me out to implement 3 short algorithms in VHDL?I am ready to pay
  • Chris Waugh
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0
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902
Chris Waugh
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ModelSim ** Warning: <foo.vhd> Choice in CASE statement alternativemust be locally static.
  • alb
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5
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Andy
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vmk and simulation
  • alb
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3
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Bart Fox
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[cross-post] vlib, vmap, vcom, how it all works...
  • alb
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0
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alb
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managing vhdl projects with Makefiles
  • alb
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7
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alb
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Newbie question on combining if rising_edge(clk).
  • mindentropy
2
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32
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KJ
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problem mixing vhdl and verilog using tristate
  • teroer
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1
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1K
teroer
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Two stage pipelining in 16-bit RISC process
  • Anoops
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1
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navneetcertain
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Change record elements
  • hssig
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3
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819
hssig
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elevator controller
  • asuraseed
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2
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916
Paul Uiterlinden
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if statement problem
  • lokesh kumar
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13
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1K
Paul Uiterlinden
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OS-VVM crosscoverage vs directed testing
  • alb
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8
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alb
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Can anyone help me out to implement some VHDL codes for some cash.
  • chris.waugh190490
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3
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chris.waugh190490
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*URGENT* Anyone keen to helpout to design a Elevator controller VHDLfile using altera *URGENT*
  • asuraseed
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1
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alb
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Conditional Compile Generate statements
  • Cory Shol
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5
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2K
Andy
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Want to understand the logic of a code
  • lkp
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0
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828
lkp
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L
Squaring of a binary number
  • lokesh kumar
2
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24
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3K
lokesh kumar
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Simulating a bidirectional bus delay
  • Fredxx
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4
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Fredxx
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Doubts on processes using a single clock.
  • mindentropy
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4
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Andy
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structured VHDL
  • alb
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11
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Andy
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Can anyone help me to design a n bit input and n bit output shift register
  • lokesh kumar
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1
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1K
goouse99
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VHDL to CMOS
  • o pere o
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7
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Theo Markettos
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Webinar: VHDL Intelligent Coverage using Open Source VHDLVerification Methodology (OSVVM), July 18
  • Jim Lewis
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0
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Jim Lewis
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The lookup table length is wrong in this description?
  • fl
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0
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802
fl
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need help to design a VHDL code from an algorithm
  • lokesh kumar
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0
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948
lokesh kumar
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counting number of reports in the message window within Modelsim
  • G buf thing
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3
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948
HT-Lab
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Need help to design n bit Galois field multiplier
  • lokesh kumar
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0
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lokesh kumar
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How can I design Galois field 2^m multiplier.
  • lokesh kumar
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4
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lokesh kumar
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[long] look up table for procedure call
  • alb
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2
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1K
alb
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VHDL, Big RGB-generator - needs shortening, algorithms
  • rik.wilmer
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3
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907
HT-Lab
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verification strategy with no specs
  • alb
Replies
4
Views
933
Rob Anderson
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