VHDL

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comp.lang.vhdl
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Cyclone III SFL Megafunction
  • Steffen Koepf
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3
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4K
Charles Steinkuehler
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EOF error.
  • Julien F.
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1
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7K
backhus
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change a clock to pulse in vhdl
  • JSreeniv
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1
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4K
Mike Treseler
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CFP: The 2010 International Conference on Modeling, Simulation, andVisualization Methods (MSV'10),
  • A. M. G. Solo
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0
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2K
A. M. G. Solo
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Noob doubt about components
  • Ricewind
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3
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8K
joris
J
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Input from file and output to file - VHDL
  • Emel
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2
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7K
nish a
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Thank you, SunMicrosystem
  • Weng Tianxiang
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3
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1K
Weng Tianxiang
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Fixed Point Binary
  • johnnyjohn2009
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0
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911
johnnyjohn2009
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How to make a Data Object Alias that's reusable
  • Hoo87
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0
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1K
Hoo87
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Use different input & output in bidirectional lines
  • nicx82
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0
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905
nicx82
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Multiple RHS values in assignment?
  • bbrady
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2
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1K
bbrady
B
A
xilinx boards
  • Amit
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2
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1K
Andy
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Identity-conversion of the clock signal
  • valentin tihhomirov
2
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21
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3K
Andy
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Request Help - Good example of resolution function
  • Daku
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4
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2K
Mike Treseler
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Verilog to VHDL sobel filter
  • pplnet
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2
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5K
pplnet
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Single process style with Xilinx
  • adamk
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9
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1K
Mike Treseler
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Conditional compiling, exists ?
  • LC
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7
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1K
LC
L
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a bit of help with enable
  • jazzman519
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0
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1K
jazzman519
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Asynchronous stuff in a cyclone III device
  • Steffen Koepf
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1
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1K
Mike Treseler
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HPCS-10 Call for papers
  • James Heralds
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0
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909
James Heralds
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issue when using to_SFix
  • axr0284
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0
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927
axr0284
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A
IEEE VHDL fixed point package
  • axr0284
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2
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3K
axr0284
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reset on cosimulation box (simulink-modelsim)
  • picnanard
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0
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1K
picnanard
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How to create an efficient two dimensional VHDL arrays table
  • tanwm
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1
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2K
KJ
K
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Discrete range in CASE
  • hssig
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17
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5K
hssig
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vhdl / verilog comparing
  • Maurice
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15
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2K
Mike Treseler
M
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easier assignment of the vector in testbench
  • milindas
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1
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1K
jerryo
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black box module integration
  • Serkan
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6
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2K
Mike Treseler
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Me and Variables Again !!!
  • LC
Replies
7
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1K
Andy
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clocking an enable input
  • jazzman519
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0
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967
jazzman519
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How to control Analog Device AD6654 in SPI mode with differentialinputs
  • tanwm
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0
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1K
tanwm
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face recognition using neural networks
  • Rash
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4
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2K
memaiaf
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Testing generic module
  • hssig
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3
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2K
hssig
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Generic for Synthesis in Synplicity
  • bruceb58
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0
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1K
bruceb58
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Q
8 bit sequential divider
  • qwerty321
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1
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4K
qwerty321
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E1 clock problem...
  • morppheu
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0
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1K
morppheu
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0
Memory controler
  • 082080112
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0
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983
082080112
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?
How you can save fuel and the environment
  • ..
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0
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1K
..
?
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Altera Quartus, libraries and mixed VHDL / (SYSTEM)VERILOG error
  • Peter Bluer
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1
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5K
Mike Treseler
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Question about checking rom
  • gioravered
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0
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897
gioravered
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Case of comparator "="
  • matchstick86
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1
Views
956
joris
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D
ored bus -- Fatal: (SIGSEGV) Bad handle or reference.
  • Diego UTN-FRP
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1
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4K
HT-Lab
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VHDL Auto-stitching tool (ala emacs verilog-mode AUTOINST)
  • Mark
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5
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5K
omara007
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Emacs VHDL-Mode Problem : vhdl-update-sensitivity-process
  • omara007
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0
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3K
omara007
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Convert text file to std_logic_vector for testbench
  • Tomeriko
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0
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1K
Tomeriko
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C program that exercises the simulated design
  • Thoma
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7
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2K
Jonathan Bromley
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Set whole row in 2D array
  • Tricky
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6
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3K
KJ
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Selecting generic at simulation time.
  • Niv (KP)
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3
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922
logic_guy
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gtkwave-3.3.0 coming soon
  • bybell
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1
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1K
bybell
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Problem with function
  • kogutu
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1
Views
926
joris
J

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