VHDL

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comp.lang.vhdl
C
inside or outside of the case statement ?
  • Calvin T
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12
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2K
prano2
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Cam
  • brijith
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1
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916
brijith
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S
Parallel LFSRs
  • sugobj
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1
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sugobj
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G
Global signal-register
  • georgemailo
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1
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926
matchstick86
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O
vhdl code for AES
  • OVIYA
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1
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2K
matchstick86
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A
Call for Papers & Sessions: The 2010 International Conference onModeling, Simulation, and Visualiza
  • A. M. G. Solo
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0
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2K
A. M. G. Solo
A
Q
vhdl loop
  • qwerty321
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0
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966
qwerty321
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M
Nice clean pulse signal
  • matchstick86
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1
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1K
matchstick86
M
M
Vhdl mouse
  • Ma7mood
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1
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2K
Ma7mood
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S
binary search has a longer combinational delay than linear search
  • sanborne
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5
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4K
Andy
A
D
Signal delay compilation error - Please Help
  • Daku
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3
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2K
Gerhard Hoffmann
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T
Insert an image in vhdl as an array
  • triggerman
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0
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1K
triggerman
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N
sensitivity list of a process
  • Nigel Noldsworth
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5
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2K
Andy
A
N
what newsgroup software you use for this VHDL group ?
  • Nigel Noldsworth
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4
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1K
Rich Webb
R
Q
max and min
  • qwerty321
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8
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2K
CS_
C
J
Timing simulation error on bus
  • JSreeniv
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3
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1K
Kenn Heinrich
K
Q
shift operations
  • qwerty321
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6
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1K
CS student
C
C
ALU code ???
  • CS_
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6
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2K
CS student
C
V
VHDL component for counting leading zeroes
  • veevee1
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0
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2K
veevee1
V
B
VHDL Code for binary/Gray counter help please
  • baigsku
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1
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2K
joris
J
D
Does VHDL support standard probability distributions
  • Daku
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1
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1K
Martin Thompson
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N
Regarding the SPI between ADC and DE2
  • New2VHDL
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1
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2K
KJ
K
Q
"condition in IF generate must be static"
  • qwerty321
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0
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3K
qwerty321
Q
Q
vhdl subtractor
  • qwerty321
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0
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2K
qwerty321
Q
Q
Alu
  • qwerty321
Replies
1
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1K
qwerty321
Q
V
A new approach to FPGA and PCB System Development Platform, SantaClara, CA, USA (By Altium)
  • Vikram
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6
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2K
rickman
R
D
Recursive structures and Quartus?
  • dgreig
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6
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2K
dgreig
D
C
Simulation : Access internal signals
  • Closter
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4
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4K
heliovj
H
P
Verilog Code to VHDL Code
  • pplnet
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0
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2K
pplnet
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N
Problem with Quartus and HI-Z signal
  • nicx82
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0
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1K
nicx82
N
K
asic
  • korte
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0
Views
888
korte
K
J
Checking to see if one second has passed
  • johnnyjohn2009
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5
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1K
jeppe
J
J
simulation limit
  • JSreeniv
Replies
3
Views
949
Thomas Stanka
T
C
"when others" clause and synthesis
  • Calvin C
Replies
6
Views
4K
JimLewis
J
K
Alias problem
  • korte
Replies
0
Views
886
korte
K
D
Co simulation of SystemC files with VHDL testbench
  • doromdor
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0
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2K
doromdor
D
H
Detecting edges of array elements
  • hssig
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3
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1K
hssig
H
C
vhdl left register
  • CS_
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1
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1K
jeppe
J
T
Adding to vector
  • thecity00
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1
Views
833
jeppe
J
G
No source after simplification, Xilinx ISE
  • golgor
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4
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2K
golgor
G
J
Alias of a bit in a 2D array
  • Joseph
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2
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3K
Mike Treseler
M
T
Displaying Digital Clock on Spartan 3e LCD
  • tarek
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0
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4K
tarek
T
H
Deferred constant in package
  • hssig
Replies
7
Views
2K
Mike Treseler
M
S
Elevator logic, pins never gets setup
  • Scorpiion
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6
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2K
Scorpiion
S
J
Digital Speedometer Design
  • johnnyjohn2009
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1
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3K
jeppe
J
D
VHDL simulator error message - please help
  • Daku
Replies
11
Views
4K
Daku
D
I
convert Verilog code to vhdl (simple program) help me please
  • imaginary
Replies
0
Views
1K
imaginary
I
M
Natural Arrays inside Records
  • mach7
Replies
0
Views
930
mach7
M
V
creating testbench template
  • Volker
Replies
2
Views
3K
Mike Treseler
M
D
Target type ieee.std_logic_1164.std_ulogic in signal assignment isdifferent frim expression type std
  • Diego UTN-FRP
Replies
4
Views
9K
Diego UTN-FRP
D

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