VHDL

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comp.lang.vhdl
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vhdl memory and Modelsim
  • ilidam
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0
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1K
ilidam
I
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Checking Files
  • Tricky
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0
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770
Tricky
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When others case and Synthesis
  • Luca D.
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0
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898
Luca D.
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Truth Table: Help !
  • marco.marsella
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2
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1K
JohnDuq
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Need some help / guidence :) VHDL/Spartan 3E
  • bogdandin7
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1
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1K
JohnDuq
J
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how to convert signal value to integer
  • Frank van Eijkelenburg
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5
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40K
vipinlal
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array ar data type in port in vhdl entity
  • lea
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2
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5K
vipinlal
V
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Expanding Integer Range in VHDL
  • Andy
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7
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14K
Andy
A
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Creating a delay with VHDL without using wait (n00b)
  • pat_jakubowski
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3
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13K
vipinlal
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VHDL--usage of WAIT statement in PROCESS
  • anil
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2
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18K
vipinlal
V
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VHDL Wait-Statement after Synthese
  • Roman
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2
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7K
vipinlal
V
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package, component, entity ......
  • u_stadler
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4
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8K
vipinlal
V
A
VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200xAdditions
  • Amal
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1
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2K
vipinlal
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CRC Error CORRECTION
  • reddy
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14
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13K
fauji86
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VHDL Test Bench + Help
  • SneakerNet
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3
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15K
vipinlal
V
S
free waveform drawing tool
  • Serkan
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10
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10K
timinganalyzer
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L
keypad encoder
  • leccy_eng
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0
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4K
leccy_eng
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Convert a signed binary number into a signed one ?
  • Rob1bureau
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1
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2K
joris
J
F
initialisation of controller
  • feng
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8
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1K
feng
F
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How a state machine is constructed using latches?
  • Weng Tianxiang
2
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23
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3K
Weng Tianxiang
W
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Array of std_logic_vector
  • Willem Oosthuizen
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3
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45K
mathukutty
M
S
array in vhdl
  • srinukasam
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6
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101K
vipinlal
V
B
generic to 0 or 1
  • Brad Smallridge
Replies
14
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1K
Brad Smallridge
B
S
timing constraint syntax/fpga editor info
  • Serkan
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2
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1K
Serkan
S
A
Call for Papers: MSV'10 (The 2010 International Conference onModeling, Simulation, and Visualizatio
  • A. M. G. Solo
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0
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1K
A. M. G. Solo
A
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Viewing intermediate variable value within a process in ModelSim
  • rwdfan
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6
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3K
Andy
A
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Call for papers: HPCS-10, Orlando, USA, July 2010
  • James Heralds
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0
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1K
James Heralds
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Legal syntax for VHDL expression
  • rickman
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1
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1K
rickman
R
R
How to write testbench file?
  • RaulGonz
2
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35
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5K
KJ
K
J
NibzW Release. Now with VGA 512*256
  • jacko
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1
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886
jacko
J
J
Anyone else noticed a change in this group?
  • James Harris
Replies
4
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831
Andy Botterill
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replacing whens with some kind of for-loop,
  • moberg2236
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1
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1K
eliascm
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B
  • Poll
Implementing division operation.
  • bhargava.ram
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0
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2K
bhargava.ram
B
B
what is incorrect about my usage of array with port entity?
  • brian_farmer
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5
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1K
Andy
A
W
The more you read, the more you are confused: about Intel's a patent
  • Weng Tianxiang
Replies
2
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1K
Eric Smith
E
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What is the basis on flip-flops replaced by a latch
  • Weng Tianxiang
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13
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4K
Weng Tianxiang
W
C
optimal no of inputs to be given in a test bench
  • chaitu
Replies
1
Views
825
Mike Treseler
M
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Draft paper submission deadline is extended: HPCS-10, Orlando, USA
  • James Heralds
Replies
0
Views
974
James Heralds
J
B
Behavioral model for a two out of five detector
  • bigmoe88
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5
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3K
bigmoe88
B
N
Problem with integer a vector range
  • nicx82
Replies
1
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2K
sridar
S
S
Modelsim
  • sridar
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0
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979
sridar
S
R
Multiple loop GENERATE
  • Ricewind
Replies
2
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808
Ricewind
R
A
CMOS Circuit Design openings with a leading firm in Bangalore, India
  • Abdul Rasheed
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0
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1K
Abdul Rasheed
A
M
Have anyone used the "justify" function successfully in questasim?
  • Magne Munkejord
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1
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1K
Magne Munkejord
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'stable operator
  • sridar
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0
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1K
sridar
S
S
Component selection in ISE
  • sridar
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0
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872
sridar
S
M
VHDL 2008: protected type
  • magne
Replies
6
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3K
magne
M
J
Draft paper submission deadline is extended: HPCS-10
  • James Heralds
Replies
0
Views
927
James Heralds
J
D
Instantiating black box module
  • Dek
Replies
3
Views
6K
Dek
D
M
vhdl2008: protected type
  • mamu
Replies
0
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1K
mamu
M

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