VHDL

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comp.lang.vhdl
S
CFP: CEC2007 Special session on: Evolutionary Computation for EDA
  • squillero
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0
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815
squillero
S
S
Different Modelsim versions disagree in same backannotation!
  • spectrallypure
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7
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3K
Paul Jansen
P
A
clock domain switch fast to slow
  • axr0284
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2
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2K
Dal
D
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NIOS II Application startup issues
  • Rob
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2
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1K
KJ
K
N
set different constants for simulation than for synthesis (preprocessor?)
  • news.sunrise
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10
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2K
Andy
A
N
avoiding division
  • nisheethg
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4
Views
946
HT-Lab
H
C
IMPLEMENTING ALU WITH OVERFLOW DETECTION ABILITY
  • chibiks
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3
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3K
Wolfgang Grafen
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Weird Modelsim warning while running backannotation
  • spectrallypure
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1
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3K
Ajeetha (www.noveldv.com)
A
C
DATA-FORWARDING IN A RISC PIPELINE
  • chibiks
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1
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2K
Mike Treseler
M
A
vhdl simulator speed test
  • Account1
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0
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827
Account1
A
K
Petri Networks - dividers of N
  • Klawy
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0
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558
Klawy
K
R
Birth date for VHDL 87 ?
  • Rick North
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2
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894
Rick North
R
G
vhdl design verified according to DO-254
  • Grzegorz
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3
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986
Grzegorz
G
Q
edif format
  • quad
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2
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3K
Wesley J. Landaker
W
K
FIFO depth?
  • krassi
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4
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4K
krassi
K
R
Is this Code synthesizable and any suggestions
  • Rama
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7
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1K
kennheinrich
K
E
Xilinx A Couple of questions
  • EE123
Replies
8
Views
907
ghelbig
G
H
Cool Runner VCCAux Question
  • Hawker
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0
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1K
Hawker
H
T
sinusoidal wave & VHDL
  • tiflis
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3
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5K
Frank Buss
F
I
Registered?
  • Ian
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2
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937
Ian
I
D
benchmarks for vhdl codes
  • dhruvakshad
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1
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928
HS
H
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PID Controllers Questions
  • Rob
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0
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1K
Rob
R
M
Illegal concurrent statement
  • Massi
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3
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19K
jetq88
J
S
Command log in MODELSIM
  • spectrallypure
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3
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4K
chriskoh
C
J
any particular things which need to be avoided?
  • jacko
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8
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1K
jacko
J
W
inserting text into a video stream (from a pre-existing video source)
  • wallge
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8
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2K
wallge
W
T
Signal wont get out of U-state ????
  • Thor Phersen
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1
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590
Mike Treseler
M
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Interlock and stall in CPU design?
  • Davy
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4
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2K
Yao Qi
Y
C
Aside from delta cycles and/or resolution functions, how can the effective value of a signal differ
  • Colin Paul Gloster
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0
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1K
Colin Paul Gloster
C
G
Simple question about if statemets
  • gman
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9
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938
Andy
A
E
error in code / ALU / calculator
  • emy86evil
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1
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3K
emy86evil
E
V
Is this Multi-Cycle Path ?
  • Ved
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1
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1K
Jim Lewis
J
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Ambiguous reference to type `UNSIGNED' - How to deal with this issue?
  • zhaoxiang.99
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3
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2K
Martin Thompson
M
E
Various FPGAs
  • EE123
Replies
3
Views
857
avishay
A
K
ALLEGRO PCB ROUTER AND ORCAD CIS, IAR Embedded.Workbench, Mentor Graphics, Tornado, VxWorks, Wind Ri
  • kashumoto_tokugawa
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1
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3K
RippedOffStockTrader2
R
I
New User Help SynaptiCad
  • Ivangray
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1
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665
Andy Peters
A
T
modulo of any number
  • Tim
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9
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1K
jens
J
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Use Multi-cycle Path or Pipeline?
  • Davy
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5
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4K
Mike Treseler
M
I
ModelSim ACTEL 6.1b help
  • Ivangray
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3
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1K
Thomas Stanka
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H
Help Needed!!!
  • Hrishi
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2
Views
687
arick.sa
A
C
VHDL design for combinational lock
  • cherryzhou21
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0
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3K
cherryzhou21
C
Y
signal spy
  • yong
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1
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3K
Ajeetha
A
V
Xilinx FIFO CoreGen: Datacount goes to zero upon full flag
  • vu_5421
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0
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927
vu_5421
V
D
DC timing violation, what to do first?
  • Davy
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9
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2K
Jim Lewis
J
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Does VHDL accept floating point design in "RTL-like" designs?
  • Mr. Ken
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6
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3K
Marcus Harnisch
M
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OT : Bug/Issue tracking systems
  • moogyd
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10
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1K
Marcus Harnisch
M
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iterative algorithms + tightly coupled CPU with cloud of logic in FPGA
  • wallge
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2
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1K
Derek Simmons
D
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undeclared identifier error message but all libraries are declaredand added (precision)
  • yttrium
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12
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5K
Jonathan Bromley
J
V
Visual IP Designer interresting new EDA tool
  • vdauthor
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4
Views
1K
vdauthor
V
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Opencore Wishbone I2C Application
  • camel_1213
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0
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1K
camel_1213
C

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