VHDL

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comp.lang.vhdl
T
double signal affectation
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1
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731
Mike Treseler
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help for "sll" shift left logical
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A
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module RGBtoYCrCb
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Jim Lewis
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VHDL test bench with quartus 2? How ?
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Writing hexadecimal to file
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ALuPin
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VHDL file IO (using file as variable)
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3K
veevee1
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VHDL assign multiple concatenated signals
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3K
veevee1
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VHDL Design Process for CMMI
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3
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2K
lyttlec
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Reading and writing the file
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0
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751
john
J
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memory element inference from variable
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0
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670
vasim98
V
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long/short sensitivity list
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1
Views
797
KJ
K
C
A Very good VLSI chip design & development website
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0
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830
chipdesignart
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M
LCD vhdl code
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1
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3K
Nicolas Matringe
N
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counter with different rates...
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2
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661
Ahmad
A
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port list order
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9
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3K
Colin Paul Gloster
C
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help about operation :s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1
  • VHDL_HELP
Replies
3
Views
784
KJ
K
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VHDL language grammar
  • titi
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2
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3K
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C
C
Difference between U, X and -
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2
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2K
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B
B
VHDL - Code verification - links
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1K
bluetoons
B
M
combinational logic in reference design
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0
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893
Mike Treseler
M
H
Any VHDL designers in Western NC
  • Hawker
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0
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739
Hawker
H
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want info on resolved signal....
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Replies
4
Views
920
Mike Treseler
M
S
list for me plz
  • siddhu_bits
Replies
1
Views
670
Colin Paul Gloster
C
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Beginner question about slice and LUT
  • Giox
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5
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1K
Martin Thompson
M
M
verilog to vhdl
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2
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1K
HT-Lab
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std_logic_vector Array Input
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5
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1K
Andy
A
P
Variable bus widths
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1
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734
KJ
K
L
verifying the c program
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0
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702
lightofspace
L
E
CRC calculation
  • edi.fraiman
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4
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2K
Marcus Harnisch
M
E
question on fifo depth...
  • ekavirsrikanth
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1
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1K
Pieter Hulshoff
P
G
Building Coaxial transmission line on PCB?
  • Geronimo Stempovski
2
Replies
35
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3K
glen herrmannsfeldt
G
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help for motion compensation
  • VHDL_HELP
Replies
1
Views
803
weber
W
J
unsigned to integer conversion
  • john
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2
Views
917
Nicolas Matringe
N
Z
convert std_logic_vector_16 to std_logic_vector_32
  • zty
Replies
0
Views
863
zty
Z
A
Call for Papers with Extended Deadline: WORLDCOMP'07 (June 25-28, 2007, Las Vegas, USA): conferenc
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0
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1K
A. M. G. Solo
A
A
synthesizable
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Replies
3
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3K
Colin Paul Gloster
C
T
Computing the width of an unsigned variable from maximum value?
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8
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5K
Torsten Landschoff
T
T
Naming conventions for signals, ports, components, instances?
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Replies
8
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2K
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T
C
needed basics of FIFO design and in writing test benches
  • chaitu
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2
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1K
JK
J
A
Call for Papers (Extended Deadline): 2007 International Conference on Modeling, Simulation and Visu
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Replies
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1K
A. M. G. Solo
A
S
Exact synatx required...!
  • shakeelsultan
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1
Views
855
rgurrola
R
D
counters in fsm
  • DualCore
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2
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1K
rgurrola
R
R
fft help
  • rgurrola
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0
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937
rgurrola
R
R
Dual Edge
  • R Quijano
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3
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2K
Ralf Hildebrandt
R
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whats wrong with this code???
  • Vineeth V
Replies
2
Views
810
R Quijano
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Wait statement in a Process
  • leeaby
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3
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1K
R Quijano
R
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Asynchronous circuitry or mixed circuitry design possible ?
  • Skybuck Flying
Replies
1
Views
951
Jan Panteltje
J
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dynamic memory allocation for images in a test bench
  • wallge
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4
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3K
wallge
W
J
How to mix verilog and vhdl files in one core
  • Jelmer
Replies
5
Views
2K
Pieter
P
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ramp generator
  • tiflis
Replies
1
Views
1K
Mike Treseler
M

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